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preliminary Data Sheet
Rev.0.9
15.11.2011
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ T CASE ≤ + 85°C; V DDQ = +1.5V ± 0.075V, V DD = +1.5V ± 0.075V)
AC CHARACTERISTICS
12800-11-11-11
10600-9-9-9
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
Unit
Clock cycle time
CL = 11
CL = 10
CL = 9
CL = 8
t CK (11)
t CK (10)
t CK (9)
t CK (8)
1.25
1.5
1.5
1.875
<1.5
<1.875
<1.875
<2.5
-
1.5
1.5
1.875
-
<1.875
<1.875
<2.5
CL = 7
CL = 6
CL = 5
Internal read command to first
data
CK high-level width
CK low-level width
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input setup time
relative to DQS V REF =1V/ns
DQ and DM input hold time
relative to DQS V REF =1V/ns
DQ and DM input pulse width
( for each input )
DQS, DQS# to DQ skew, per
access
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
DQS input high pulse width
DQS input low pulse width
DQS, DQS# rising to/from CK,
CK#
DQS, DQS# rising to/from CK,
CK# when DLL disabled
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
associated clock edge
Address and control input pulse
width ( for each input )
CTRL, CMD, Addr setup to CK,
CK#
CTRL, CMD, Addr setup to CK,
CK# V REF @ 1V/ns
t CK (7)
t CK (6)
t CK (5)
t AA
t CH (avg)
t CL (avg)
t HZ
t LZ
t DS1V
t DH1V
t DIPW
t DQSQ
t QH
t DQSH
t DQSL
t DQSCK
t DQSCK
DLL_DIS
t DSS
t DSH
t RPRE
t RPST
t WPRE
t WPST
t DQSS
t IPW
t IS(Base)
t IS(1V)
1.875
2.5
3.0
13.75
0.47
0.47
-
-450
160
145
360
0.38
0.45
0.45
-225
1
0.18
0.18
0.9
0.3
0.9
0.3
- 0.27
560
45
220
<2.5
3.3
3.3
20
0.53
0.53
225
225
-
-
-
100
-
0.55
0.55
225
10
-
-
Note1
Note2
-
-
+ 0.27
-
-
-
1.875
2.5
3.0
13.5
0.47
0.47
-
-500
180
165
400
-
0.38
0.45
0.45
-255
1
0.2
0.2
0.9
0.3
0.9
0.3
- 0.25
620
65
240
<2.5
3.3
3.3
20
0.53
0.53
250
250
-
-
-
125
-
0.55
0.55
255
10
-
-
Note1
Note2
-
-
+ 0.25
-
-
-
ns
t CK
t CK
ps
ps
ps
ps
ps
ps
t CK
(AVG)
t CK
t CK
ps
ns
t CK
t CK
t CK
t CK
t CK
t CK
t CK
ps
ps
ps
1
2
The maximum preamble is bound by t LZDQS (MAX)
The maximum postamble is bound by t HZDQS (MAX)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
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